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<html xmlns="http://www.w3.org/1999/xhtml"><head><link rel="stylesheet" type="text/css" href="insn.css"/><meta name="generator" content="iform.xsl"/><title>RPRFM -- A64</title></head><body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">RPRFM</h2>
      <p class="aml">Range Prefetch Memory signals the memory system that data memory accesses from a specified range of addresses are likely to occur in the near future. The instruction may also signal the memory system about the likelihood of data reuse of the specified range of addresses. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as prefetching locations within the specified address ranges into one or more caches. The memory system may also exploit the data reuse hints to decide whether to retain the data in other caches upon eviction from the innermost caches or to discard it.</p>
      <p class="aml">The effect of an <span class="asm-code">RPRFM</span> instruction is <span class="arm-defined-word">implementation defined</span>, but because these signals are only hints, the instruction cannot cause a synchronous Data Abort exception and is guaranteed not to access Device memory. It is valid for the PE to treat this instruction as a NOP.</p>
      <p class="aml">An <span class="asm-code">RPRFM</span> instruction specifies the type of accesses and range of addresses using the following parameters:</p>
      <ul>
        <li>'Type', in the &lt;rprfop&gt; operand opcode bits, specifies whether the prefetched data will be accessed by load or store instructions.</li>
        <li>'Policy', in the &lt;rprfop&gt; operand opcode bits, specifies whether the data is likely to be reused or if it is a streaming, non-temporal prefetch. If a streaming prefetch is specified, then the 'ReuseDistance' parameter is ignored.</li>
        <li>'BaseAddress', in the 64-bit base register, holds the initial block address for the accesses.</li>
        <li>'ReuseDistance', in the metadata register bits[63:60], indicates the maximum number of bytes to be accessed by this PE before executing the next <span class="asm-code">RPRFM</span> instruction that specifies the same range. This includes the total number of bytes inside and outside of the range that will be accessed by the same PE. This parameter can be used to influence cache eviction and replacement policies, in order to retain the data in the most optimal levels of the memory hierarchy after each access. If software cannot easily determine the amount of other memory that will be accessed, these bits can be set to zero to indicate that 'ReuseDistance' is not known. Otherwise, these four bits encode decreasing powers of two in the range 512MiB (0b0001) to 32KiB (0b1111).</li>
        <li>'Stride', in the metadata register bits[59:38], is a signed, two's complement integer encoding of the number of bytes to advance the block address after 'Length' bytes have been accessed, in the range -2MiB to +2MiB-1B. A negative value indicates that the block address is advanced in a descending direction.</li>
        <li>'Count', in the metadata register bits[37:22], is an unsigned integer encoding of the number of blocks of data to be accessed minus 1, representing the range 1 to 65536 blocks. If 'Count' is 0, then the 'Stride' parameter is ignored and only a single block of contiguous bytes from 'BaseAddress' to ('BaseAddress' + 'Length' - 1) is described.</li>
        <li>'Length', in the metadata register bits[21:0], is a signed, two's complement integer encoding of the number of contiguous bytes to be accessed starting from the current block address, without changing the block address, in the range -2MiB to +2MiB-1B. A negative value indicates that the bytes are accessed in a descending direction.</li>
      </ul>
      <div class="note"><hr class="note"/><h4>Note</h4>
        <p class="aml">Software is expected to honor the parameters it provides to the <span class="asm-code">RPRFM</span> instruction, and the same PE should access all locations in the range, in the direction specified by the sign of the 'Length' and 'Stride' parameters. A range prefetch is considered active on a PE until all locations in the range have been accessed by the PE. A range prefetch might also be inactivated by the PE prior to completion, for example due to a software context switch or lack of hardware resources.</p>
        <p class="aml">Software should not specify overlapping addresses in multiple active ranges. If a range is expected to be accessed by both load and store instructions (read-modify-write), then a single range with a 'Type' parameter of PST (prefetch for store) should be specified.</p>
      <hr class="note"/></div>
    
    <h3 class="classheading"><a id="iclass_general"/>Integer<span style="font-size:smaller;"><br/>(FEAT_RPRFM)
          </span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td class="r">1</td><td class="l">1</td><td>1</td><td class="r">1</td><td class="lr">0</td><td class="l">0</td><td class="r">0</td><td class="l">1</td><td class="r">0</td><td class="lr">1</td><td colspan="5" class="lr">Rm</td><td class="l">x</td><td>1</td><td class="r">x</td><td class="lr">S</td><td class="l">1</td><td class="r">0</td><td colspan="5" class="lr">Rn</td><td class="l">1</td><td>1</td><td>x</td><td>x</td><td class="r">x</td></tr><tr class="secondrow"><td colspan="2" class="droppedname">size</td><td colspan="3"/><td/><td colspan="2"/><td colspan="2" class="droppedname">opc</td><td/><td colspan="5"/><td colspan="3" class="droppedname">option</td><td/><td colspan="2"/><td colspan="5"/><td colspan="5" class="droppedname">Rt</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="RPRFM_R_ldst_regoff"/><p class="asm-code">RPRFM  (<a href="#sa_rprfop" title="Range prefetch operation, defined as {syntax{&lt;type&gt;&lt;policy&gt;}} (field &quot;Rt&lt;0&gt;&quot;)">&lt;rprfop&gt;</a>|#<a href="#sa_imm6" title="Range prefetch operation encoding as an immediate [0-63] (field &quot;option&lt;2&gt;:option&lt;0&gt;:S:Rt&lt;2:0&gt;&quot;)">&lt;imm6&gt;</a>), <a href="#sa_xm" title="64-bit general-purpose register that holds an encoding of metadata (field &quot;Rm&quot;)">&lt;Xm&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>]</p></div><p class="pseudocode">bits(6) operation = option&lt;2&gt;:option&lt;0&gt;:S:Rt&lt;2:0&gt;;
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rm);</p>
  <div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;rprfop&gt;</td><td><a id="sa_rprfop"/>
        
          <p class="aml">Is the range prefetch operation, defined as &lt;type&gt;&lt;policy&gt;.</p>
          <p class="aml">&lt;type&gt; is one of:</p>
          <dl>
            <dt>PLD</dt><dd>Prefetch for load, encoded in the "Rt&lt;0&gt;" field as 0.</dd>
            <dt>PST</dt><dd>Prefetch for store, encoded in the "Rt&lt;0&gt;" field as 1.</dd>
          </dl>
          <p class="aml">&lt;policy&gt; is one of:</p>
          <dl>
            <dt>KEEP</dt><dd>Retained or temporal prefetch, for data that is expected to be kept in caches to be accessed more than once, encoded in the "option&lt;2&gt;:option&lt;0&gt;:S:Rt&lt;2:1&gt;" fields as 0b00000.</dd>
            <dt>STRM</dt><dd>Streaming or non-temporal prefetch, for data that is expected to be accessed once and not reused, encoded in the "option&lt;2&gt;:option&lt;0&gt;:S:Rt&lt;2:1&gt;" fields as 0b00010.</dd>
          </dl>
          <p class="aml">For other encodings of the "option&lt;2&gt;:option&lt;0&gt;:S:Rt&lt;2:0&gt;" fields, use &lt;imm6&gt;.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;imm6&gt;</td><td><a id="sa_imm6"/>
        
          <p class="aml">Is the range prefetch operation encoding as an immediate, in the range 0 to 63, encoded in "option&lt;2&gt;:option&lt;0&gt;:S:Rt&lt;2:0&gt;". This syntax is only for encodings that are not representable using &lt;rprfop&gt;.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Xm&gt;</td><td><a id="sa_xm"/>
        
          <p class="aml">Is the 64-bit name of the general-purpose register that holds an encoding of the metadata, encoded in the "Rm" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Xn|SP&gt;</td><td><a id="sa_xn_sp"/>
        
          <p class="aml">Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</p>
        
      </td></tr></table></div><div class="syntax-notes"/>
    <div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3>
      <p class="pseudocode">bits(64) address = if n == 31 then <a href="shared_pseudocode.html#impl-aarch64.SP.read.0" title="accessor: bits(64) SP[]">SP</a>[] else <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];
bits(64) metadata = <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[m, 64];
integer stride = <a href="shared_pseudocode.html#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(metadata&lt;59:38&gt;);
integer count = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(metadata&lt;37:22&gt;) + 1;
integer length = <a href="shared_pseudocode.html#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(metadata&lt;21:0&gt;);
integer reuse;

if metadata&lt;63:60&gt; == '0000' then
    reuse = -1;    // Not known
else
    reuse = 32768 &lt;&lt; (15 - <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(metadata&lt;63:60&gt;));

<a href="shared_pseudocode.html#impl-shared.Hint_RangePrefetch.6" title="function: Hint_RangePrefetch(bits(64) address, integer length, integer stride, integer count, integer reuse, bits(6) operation)">Hint_RangePrefetch</a>(address, length, stride, count, reuse, operation);</p>
    </div>
  <hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
      Internal version only: isa v33.62, AdvSIMD v29.12, pseudocode v2023-03_rel, sve v2023-03_rc3b
      ; Build timestamp: 2023-03-31T11:36
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